Chip-level equalizers (CLE) are suitable candidates for CDMA receivers, such as those used in wireless transmit/receive units (WTRUs) and base stations. An NLMS-based CLE receiver offers superior performance for high data rate services such as high speed downlink packet access (HSDPA) over a Rake receiver. A typical NLMS receiver comprises an equalizer filter and an NLMS algorithm. The equalizer filter is typically a finite impulse response (FIR) filter.
The NLMS algorithm is used for tap-weights generation. It generates appropriate tap-weights used by the equalizer filter and updates them appropriately and iteratively in a timely basis. Typically, tap-weights generation includes error signal computation, vector norm calculation and leaky integration to generate and update the tap-weights.
The high complexity of the CLE is due to the over-sampling processing in the CLE. A typical process in the CLE equalizer includes filtering, tap-weight vector updating, vector norm square computing, or the like, which all operate at two or more times the chip rate. Two times the chip rate over-sampling processing induces twice as much complexity as the chip rate non-over-sampling processing in the equalizer filter.
Particularly, multiplications of a tap-input vector with tap-weights which are performed on a chip-by-chip basis are usually the component with major complexity and results in high complexity.